1. Field of the Invention
The present invention relates to an etching method, a method of manufacturing a semiconductor device, and a semiconductor device.
2. Description of Related Art
In a semiconductor process, a processing technique for etching a material film formed on a substrate is necessary.
The etching technique may be roughly classified into two kinds: a wet etching which uses a chemical solution including an acid as an etching solution (etchant); and a dry etching which uses various gases. Moreover, as for the wet etching, a dipping method which dips the substrate, such as a wafer or the like, into the etchant, and a spinning method which drops the chemical solution into the substrate and carries out the etching while rotating the substrate, and the like are known. Furthermore, as the etchant for a semi-insulating GaAs substrate used for a field effect transistor, which will be described later, and the like, the mixed solution of organic acid, such as phosphoric acid, citric acid and the like, hydrogen peroxide and water is typically used.
When the wet etching is used to etch a substrate, its etching amount typically depends on an etching time. That is, the dipping method tries to obtain a predetermined etching amount by dipping the substrate into the etchant for a predetermined time.
As one of the semiconductor processes which use the above-mentioned wet etching, there is a method of manufacturing a semiconductor device, which is designed to form a plurality of transistors having different threshold voltages on the same semiconductor substrate (for example, see Japanese Patent Application Publication 2002-100641).
When the plurality of transistors are assumed to be a depletion type field effect transistor (hereafter, referred to as D-FET and an enhancement type field effect transistor (hereafter, referred to as E-FET), in which threshold voltages are different from each other, their configurations are simply explained.
FIG. 6 shows an example of IC in which the D-FET and the E-FET are formed on the same substrate. By the way, for the purpose of explanation, it is explained under the assumption that the E-FET is arranged on the right side of each drawing and the D-FET is arranged on the left side thereof.
In FIG. 6, a numeral 100 indicates a semi-insulating GaAs substrate. A buffer layer 110, a channel layer 120 and a barrier layer 130 are formed thereon in order of mention by epitaxial growth. The barrier layer 130 is constructed from: a spacer layer 131 made of undoped AlGaAs; an electron supplying layer 132 made of AlGaAs in which, for example, n-type impurity is doped; and a gate contact layer 133 made of undoped AlGaAs. A first buried gate region 141 to which, for example, p-type impurity is added at a high concentration (the E-FET side) and a second buried gate region 142 (the D-FET side) are formed in this gate contact layer 133, respectively. By the way, a numeral 150 indicates an insulating film, numerals 161, 171 indicate a source electrode and a drain electrode on the E-FET side, numerals 162, 172 indicate a source electrode and a drain electrode on the D-FET side, and numerals 181, 182 indicate gate electrodes on the E-FET side and the D-FET, respectively.
Here, it is known that the respective threshold voltages of the E-FET and the D-FET are determined from the distances between the respective buried gate regions 141, 142 and the electron supplying layer 132.
The buried gate region 142 immediately under the gate electrode 182 on the D-FET side is formed such that, for example, the portion on the insulating film 150 is used as mask, and the p-type impurity is selectively diffused from its gate opening 152. Next, the depth from the surface thereof is controlled so as to exhibit any threshold voltage.
On the other hand, the first buried gate region 141 located immediately under the gate electrode 181 on the E-FET side is formed such that as for the gate contact layer 133 exposed to the gate opening 151 formed in the insulating film 150, as shown in FIG. 7, after a resist 190 is formed on the surface, for example, the above-mentioned wet etching is used to selectively carry out the etching and reduce the layer thickness, and, simultaneously with the formation of the second buried gate region 142 on the D-FET side, the p-type impurity is selectively diffused. That is, the thickness of the gate contact layer 133 on which the first buried gate region 141 is formed is adjusted so as to obtain a predetermined threshold voltage when the p-type impurity having the same depth as the D-FET side is diffused.